This technology described herein relates to graphics processing systems, and in particular to tile-based graphics processing systems.
Graphics processing systems may use so-called “tile-based” rendering. In tile based rendering, the, e.g., two dimensional, output array or frame of the rendering process (the “render target”) (e.g., and typically, that will be displayed to display a scene that is being rendered) is sub-divided or partitioned into a plurality of smaller sub-regions, usually referred to as “tiles”, for the rendering process. The tiles (sub-regions) are each rendered separately (typically one after another). The rendered tiles (sub-regions) are then recombined to provide the complete output array (frame) (render target), e.g. for display.
The tiles can therefore be thought of as the sub divisions of the render target area (output frame) that the rendering process operates on. In such arrangements, the render target area (output frame) is typically divided into regularly sized and shaped tiles (they are usually, e.g., squares or rectangles) but this is not essential.
Each tile will comprise a block (array) of sampling positions and may be any suitable and desired size, but is typically a block of 16×16 sampling positions or 32×8 sampling positions. (Each sampling position in the tile, e.g. for which rendered fragment data is generated, may be the same size and location as a “pixel” of the output (e.g. output frame) (since as the pixels are the singularities in the final display, there may be a one-to-one mapping between the sampling positions the rendering circuitry renders and the pixels of a display). However, it can be the case that there is not a one-to-one correspondence between a sampling position and a display pixel, for example where particular forms of post-processing, such as downsampling, are carried out on the rendered image prior to displaying the final image.)
Other terms that are commonly used for “tiling” and “tile-based” rendering include “chunking” (the sub-regions are referred to as “chunks”) and “bucket” rendering. The terms “tile” and “tiling” will be used herein for convenience, but it should be understood that these terms are intended to encompass all alternative and equivalent terms and techniques.
In tile-based graphics processing, sampling positions for a tile are rendered to derive a set of rendered graphics data, such as red, green and blue (RGB) colour values and an “alpha” (transparency) value (or corresponding values in other colour spaces, e.g. YUV components, or other data values that may be generated for sampling positions using a graphics processing pipeline), necessary to represent each sampling position, e.g. for display.
Graphics processing systems and graphics processors are typically provided in the form of graphics processing pipelines which have multiple processing stages for performing the graphics processing functions, such as fetching input data, geometry processing, vertex shading, rasterisation, rendering, etc., necessary to generate the desired set of output graphics data.
A tile-based graphics processing pipeline will also include one or more so-called tile buffers that store rendered sampling position data at the end of the pipeline until a given tile is completed and written out to an external memory, such as a frame buffer, for use, e.g. in displaying the output frame. This local, pipeline memory is used to retain rendered sampling position data locally before the data is finally exported to external memory.
In order to facilitate the writing back of rendered graphics data from the tile buffers to external memory, such as a frame buffer, a graphics processing pipeline will typically include write out circuitry coupled to the tile buffer pipeline memory for this purpose.
One issue that arises in the context of graphics processors, particularly for graphics processors that are to be used in lower power and portable devices, is the bandwidth cost of writing data to external memory from the graphics processing pipeline. Bandwidth consumption can be a big source of heat and of power consumption, and so it is generally desirable to try to reduce bandwidth consumption for external memory writes in graphics processing systems.
In order to try to reduce the bandwidth consumption for external memory writes in graphics processing systems, frame buffer compression techniques may be used to try to reduce the amount of data that is required to be written to the frame buffer. Such compression techniques may, inter alia, attempt to identify, when reading the fragment data in the tile buffer for writing to the frame buffer, blocks of sampling positions, e.g. the whole tile, for which the colour is constant across the block.
One such frame buffer compression technique is described in the Applicant's U.S. Pat. No. 8,542,939 B2, U.S. Pat. No. 9,014,496 B2, U.S. Pat. No. 8,990,518 B2 and U.S. Pat. No. 9,116,790 B2.
Identifying such blocks of constant colour may enable the colour data for the block of sampling positions to be more efficiently compressed for storing in the frame buffer, e.g. by writing out to the frame buffer only a single colour value for the block of sampling positions having the same colour rather than storing a separate colour value for each sampling position in the block. This may allow the amount of information that needs to be written out to the frame buffer and stored for the tile (and thus processed when displaying the tile) to be reduced.
Notwithstanding these known techniques, the Applicants believe that there remains scope for further improvements for reducing bandwidth consumption by graphics processing pipelines, and in particular by tile-based graphics processors when performing real-time graphics processing operations.